The invention relates to a power semiconductor array on a direct copper bonding (DCB) substrate which includes a first intermediate circuit terminal connected to a positive potential, a second intermediate circuit terminal connected to a negative potential, and at least one load terminal. The power semiconductor array further has at least two power switches for connecting the load terminal to the first and second intermediate circuit terminals in alternation. Such power semiconductor arrays serve as a power part for contactless energy conversion to suit a target function, for instance in drive power converters with rpm governing, interrupt-free power supplies, in electroplating and for use in welding current courses, and so forth. To that end, energy is drawn from the supply terminals (intermediate circuit terminals) of the power semiconductor arrays to suit the desired power flow and is supplied to the applicable load, and then fed back from the load to the intermediate circuit. Thus the intermediate circuit is a buffer store for energy, for instance in the form of a capacitor battery. The invention is especially well suited to such an application, but is not limited to it.
In the prior art, the actual semiconductor chip in the power semiconductor array is joined via solder to a first copper layer, which is mounted in turn on a ceramic insulator. The ceramic insulator is joined to the bottom plate of the structure via a second copper layer and solder. The bottom plate serves to mount the array mechanically on a cooling body and for touch protection is usually resting on ground (protective ground).
Power electronic circuits of this kind, which operate on the basis of fast switching events on the principle of energy conversion through switching, cause a high degree of electromagnetic interference emission. The limits of maximum interference emission prescribed in some standards (such as 50081/1/2) are then far exceeded and require major expenditure for interference suppression. When the power semiconductor array of the prior art is used, among other provisions, expensive external circuits are therefore required, which filter out the interference currents or voltages that are caused by the fast switching.
It is accordingly an object of the invention to provide a power semiconductor array on a DCB substrate that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the interference emissions propagated over its terminal lines are eliminated, or at least sharply reduced, directly on the semiconductor device.
With the foregoing and other objects in view there is provided, in accordance with the invention, a power semiconductor array on a direct copper bonding substrate, including:
terminals including a first intermediate circuit terminal to be connected to a positive potential, a second intermediate circuit terminal to be connected to a negative potential, at least one load terminal, and a ground terminal;
at least two power switches, including a first power switch and a second power switch, connecting the at least one load terminal to the first and second intermediate circuit terminals in alternation;
an insulation layer having a conductive intermediate layer disposed therein;
connections that capacitively connect at least some of the terminals that lead to an outside to one another in pairs, and the ground terminal leading to the outside is capacitively connected to the at least one load terminal via the insulation layer, and the conductive intermediate layer connected to one of the first and second intermediate circuit terminals.
The principle on which the invention is based is thus to reduce the interference by short-circuiting parasitic interference current paths within the power semiconductor array.
In a preferred embodiment of the power semiconductor array, a connecting line between the first intermediate circuit terminal and the first power switch and a connecting line between the second intermediate circuit terminal and the second power switch are disposed such that the two intermediate circuit terminals are capacitively connected to one another.
A ground terminal leading to the outside can also be provided; the load terminal is capacitively connected to the ground terminal via an insulation layer, and the insulation layer has a conductive intermediate layer that is connected to the first or second intermediate circuit terminal. The intermediate layer preferably is formed of copper or a copper alloy.
The power semiconductor array of the invention can also have a driver stage for triggering the power switches with two driver supply terminals, and the driver supply terminals are connected capacitively and/or galvanically with at least one of the intermediate circuit terminals. (The term xe2x80x9cgalvanic bondingxe2x80x9d is understood hereinafter to be a direct electrical connection, with negligibly slight or finite ohmic resistance, in contrast to a capacitive or inductive connection.) In addition to a capacitive coupling, the driver supply terminals of the driver stage can be inductively coupled to one another.
The power switches of the power semiconductor array can be active or passive power switches. The power switches can also each include a plurality of power switch elements, to increase the total attainable switching capacity. The individual active power switch elements can additionally include reverse diodes connected parallel to the switching path.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a power semiconductor array on a DCB substrate, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.